1. Field of the Invention
The invention relates generally to a semiconductor memory storage system and its method of operation.
More particularly the invention relates to a system in which both the read/write circutis and restore/recovery circuits are coupled to the storage cells via the bit lines and whose read/write cycles are performed in several phases.
2. Description of the Prior Art
Present memory systems and in particular those used for computer applications are manufactured using integrated semiconductor technology, and as such comprise a plurality of specifically organized memory storage cells formed in monolithic semiconductor chips.
Such storage cells have been designed using flip flop circuits having bipolar transistors as the switching transistors, Schottky diodes as the read/write elements coupling the cell to the bit lines and high-resistivity resistors as the load elements. Such a cell is shown, for example, in the IBM Technical Disclosure Bulletin, Vol. 16, No. 6, November 1973, on pages 1920 to 1921. This cell when used as described has the disadvantage that the cell node potentials are not sufficiently rapidly raised to values such that the cell can be affected by read/write operations of adjacent storage cells. As a result, a relatively long time has to elapse before the next read/write cycle can be initiated, thus a system using the described cell will have relatively long read/write cycles.
A monolithic storage cell with two base-collector cross-coupled transistors having a collector resistor, with a relatively high resistivity, and one diode per transistor connected parallel thereto, whereby the resistor is designed as a pinch resistor is also known. The design of the pinch resistor is such that the collector resistor belonging to the circuit of one transistor of the cell is designed as a resistor buried under the emitter material in the extension of the base zone of the other transistor, and the diode is connected parallel to the collector resistor of one transistor being formed by the base-collector junction of the other collector resistor. Although this described cell is highly integratable, it has the disadvantage that the cell node potentials are raised only slowly to values at which the cell is not affected by read/write operations of adjacent storage cells, so that the read/write cycle is very long. These pinch resistors have the further disadvantage of leading to a relatively high storage cell current and relatively high power dissipation, respectively, so that from the thermal standpoint, higher integration densities on the storage chip are limited.
In order to reduce the storage cell currents and thus the power dissipation, it would, in principle, be possible to use bipolar transistors instead of pinch resistors as load elements. Although from a thermal standpoint this would permit a higher integration density, the reduced storage cell current would delay still further the charging of the storage cell nodes after selection of a storage cell, thus substantially prolonging the read or write cycles.